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| 4-STAGE SYNCHRONOUS BIDIRECTIONAL COUNTERS The MC54/74F168 and MC54/74F169 are fully synchronous 4-stage up/ down counters. The F168 is a BCD decade counter; the F169 is a modulo-16 binary counter. Both feature a preset capability for programmable operation, carry lookahead for easy cascading, and a U/D input to control the direction of counting. All state changes, whether in counting or parallel loading, are initiated by the LOW-to-HIGH transition of the clock. * Asynchronous Counting and Loading * Built-In Lookahead Carry Capability * Presettable for Programmable Operation CONNECTION DIAGRAM (TOP VIEW) VCC 16 TC 15 Q0 14 Q1 13 Q2 12 Q3 11 CET 10 PE 9 16 MC54/74F168 MC54/74F169 4-STAGE SYNCHRONOUS BIDIRECTIONAL COUNTERS FASTTM SCHOTTKY TTL J SUFFIX CERAMIC CASE 620-09 1 16 N SUFFIX PLASTIC CASE 648-08 1 1 U/D 2 CP 3 P0 4 P1 5 P2 6 P3 7 CEP 8 GND MODE SELECT TABLE PE L H H H H CEP X L L H X CET X L L X H U/D X H L X X Action on Rising Clock Edge Qn) Count Up (Increment) Count Down (Decrement) No Change (Hold) No Change (Hold) Load (Pn 16 1 D SUFFIX SOIC CASE 751B-03 ORDERING INFORMATION MC54FXXXJ MC74FXXXN MC74FXXXD Ceramic Plastic SOIC H = HIGH Voltage Level; L = LOW Voltage Level; X = Don't Care STATE DIAGRAMS MC54/74F169 0 1 2 3 4 LOGIC SYMBOL 93456 PE P0 P1 P2 P3 U/D CEP TC CET CP Q0 Q1 Q2 Q3 14 13 12 11 MC54/74F168 0 1 2 3 15 5 1 7 10 2 10 9 11 15 4 14 13 14 6 15 13 7 VCC = Pin 16 GND = Pin 8 8 7 6 5 12 12 11 10 9 8 COUNT DOWN COUNT UP COUNT DOWN COUNT UP FAST AND LS TTL DATA 4-82 MC54/74F168 * MC54/74F169 LOGIC DIAGRAMS MC54/74F168 PE CEP CET P0 P1 P2 P3 T LD AT AF TC LD T BT BF UP DN DETAIL A ENF CP Q ENF U/D UP DN DETAIL A DETAIL A CP CP DETAIL A Q Q0 J CP K Q Q Q1 Q2 Q3 MC54/74F169 PE CEP CET P0 P1 P2 P3 T LD AT AF TC LD T BT BF ENF U/D UP DN UP DN DETAIL A ENF CP DETAIL A J CP K Q Q CP Q DETAIL A DETAIL A CP Q NOTE: These diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays. Q0 Q1 Q2 Q3 FAST AND LS TTL DATA 4-83 MC54/74F168 * MC54/74F169 FUNCTIONAL DESCRIPTION The F168 and F169 use edge-triggered J-K type flip-flops and have no constraints on changing the control or data input signals in either state of the clock. The only requirement is that the various inputs attain the desired state at least a setup time before the rising edge of the clock and remain valid for the recommended hold time thereafter. The parallel load operation takes precedence over other operations, as indicated in the Mode Select Table. When PE is LOW, the data on the P0-P3 inputs enters the flip-flops on the next rising edge of the clock. In order for counting to occur, both CEP and CET must be LOW and PE must be HIGH; the U/D input then determines the direction of counting. The Terminal Count (TC) output is normally HIGH and goes LOW, provided that CET is LOW, when a counter reaches zero in the Count Down mode or reaches 9 (15 for the F169) in the Count Up mode. The TC GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current -- High Output Current -- Low Parameter 54, 74 54 74 54, 74 54, 74 Min 4.5 -55 0 Typ 5.0 25 25 Max 5.5 125 70 -1.0 20 mA mA Unit V C output state is not a function of the Count Enable Parallel (CEP) input level. The TC output of the F168 decade counter can also be LOW in the illegal states 11, 13, and 15, which can occur when power is turned on or via parallel loading. If an illegal state occurs, the F168 will return to the legitimate sequence within two counts. Since the TC signal is derived by decoding the flip-flop states, there exists the possibility of decoding spikes on TC. For this reason the use of TC as a clock signal is not recommended (see logic equations below). 1) Count Enable = CEP * CET * PE 2) Up: (F168): TC = Q0 * Q1 * Q2 * Q3 * (Up) * CET (F169): TC = Q0 * Q1 * Q2 * Q3 * (Up) * CET 3) Down: TC = Q0 * Q1 * Q2 * Q3 * (Down) * CET DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 54, 74 74 VOL IIH Output LOW Voltage Input HIGH Current 2.5 2.7 3.4 3.4 0.35 0.5 20 0.1 Input LOW Current IIL IOS ICC CET Other Inputs Output Short Circuit Current (Note 2) Power Supply Current -60 -1.2 -0.6 -150 52 mA mA VCC= MAX, VOUT = 0 V VCC = MAX mA VCC = MAX, VIN = 0.5 V Min 2.0 0.8 -1.2 Typ Max Unit V V V V V V A mA Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VCC = MIN, IIN = - 18 mA IOH = - 1.0 mA IOH = - 1.0 mA IOL = 20 mA VCC = 4.50 V VCC = 4.75 V VCC = MIN VCC = MAX, VIN = 2.7 V VCC = MAX, VIN = 7.0 V NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable device type. 2. Not more than one output should be shorted at a time, nor for more than 1 second. FAST AND LS TTL DATA 4-84 MC54/74F168 * MC54/74F169 AC CHARACTERISTICS 54/74F TA = +25C VCC = +5.0 V CL = 50 pF Symbol fmax tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Parameter Maximum Clock Frequency Propagation Delay CP to Qn (PE HIGH or LOW) Propagation Delay CP to TC Propagation Delay CP to TC Propagation Delay CET to TC Propagation Delay U/D to TC Propagation Delay U/D to TC (F169) (F168) (F169) (F168) Min 100 3.0 4.0 5.5 4.0 5.0 4.0 2.5 2.5 3.5 4.0 3.5 4.0 8.5 11.5 15.5 11 15.5 11 6.0 8.0 11 16 11 10.5 Max 60 3.0 4.0 5.5 4.0 5.0 4.0 2.5 2.5 3.5 4.0 3.5 4.0 10.5 14 18 13.5 18 13.5 8.0 10 13.5 18.5 13.5 13 54F TA = -55C to +125C VCC = 5.0 V 10% CL = 50 pF Min Max 74F TA = 0C to 70C VCC = 5.0 V 10% CL = 50 pF Min 85 3.0 4.0 5.5 4.0 5.0 4.0 2.5 2.5 3.5 4.0 3.5 4.0 9.5 13 17 12.5 17 12.5 7.0 9.0 12.5 17.5 12.5 12 Max Unit MHz ns ns ns ns ns ns AC OPERATING REQUIREMENTS 54/74F TA = +25C VCC = +5.0 V Symbol ts(H) ts(L) th(H) th(L) ts(H) ts(L) th(H) th(L) ts(H) ts(L) th(H) th(L) ts(H) ts(L) ts(H) ts(L) th(H) th(L) tw(H) tw(L) Parameter Setup Time, HIGH or LOW Pn to CP Hold Time, HIGH or LOW Pn to CP Setup Time, HIGH or LOW CEP or CET to CP Hold Time HIGH or LOW CEP or CET to CP Setup Time, HIGH or LOW PE to CP Hold Time, HIGH or LOW PE to CP Setup Time, HIGH or LOW (F168) U/D to CP Setup Time, HIGH or LOW (F169) U/D to CP Hold time, HIGH or LOW U/D to CP CP Pulse Width HIGH or LOW Min 4.0 4.0 3.0 3.0 5.0 5.0 0 0 8.0 8.0 0 0 11 16.5 11 7.0 0 0 5.0 5.0 Max 54F TA = -55C to +125C VCC = 5.0 V 10% Min 5.5 5.5 3.5 3.5 7.0 7.0 0 0 10 10 0 0 13.5 19 13.5 9.0 0 0 8.0 8.0 Max 74F TA = 0C to 70C VCC = 5.0 V 10% Min 4.5 4.5 3.5 3.5 6.0 6.0 0 0 9.0 9.0 0 0 12.5 18 12.5 8.0 0 0 5.5 5.5 Max Unit ns ns ns ns ns ns ns ns ns ns FAST AND LS TTL DATA 4-85 |
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